URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] - Rev 66

Rev	Log message	Author	Age	Path
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6359d 14h	/
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6359d 14h	/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6360d 12h	/
43	Added welcome message as a remainder to set paths for tools!=IVerilog	fafa1971	6360d 12h	/
42	Added support for filelist for Xilinx ISE XST synthesis	fafa1971	6360d 12h	/
41	Added copy of empty modules upon original SPARC copies	fafa1971	6360d 12h	/
40	First version of synthesis script for Xilinx ISE XST	fafa1971	6360d 12h	/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6360d 12h	/
38	Changed to compile (for now) the boot code.	fafa1971	6364d 11h	/
37	Memory image coming from the new boot.s	fafa1971	6364d 11h	/