OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 151

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
131 SdClockMaster added to regression tests rkastl 4948d 01h /
130 SdClockMaster: Formal verification rkastl 4948d 01h /
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4948d 01h /
128 Sim: Support for psl files added. rkastl 4948d 01h /
127 Thesis: Restructured SDHC chapter. rkastl 4948d 01h /
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4948d 01h /
125 Write works in simulation rkastl 4948d 01h /
124 Write: SdClk is disabled, if no data is available. rkastl 4948d 01h /
123 Write: Must be able to halt SdClk, rest is done. rkastl 4948d 01h /
122 SdController: Initial read support rkastl 4948d 04h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.