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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4508d 15h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4508d 17h /
42 Bug fix in read access is fixed dinesha 4508d 17h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4508d 19h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4509d 12h /
39 Test Bench upgradation with bigger data burst size dinesha 4509d 12h /
38 Port Name clean up dinesha 4510d 17h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4510d 19h /
36 Clean up dinesha 4511d 09h /
35 Updated the New Documents - ver 0.1 dinesha 4511d 11h /

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