URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 72

Rev	Log message	Author	Age	Path
52	Documentation update for request control and transfer control block	dinesha	4503d 23h	/
51	FPGA relating timing optimisation done	dinesha	4504d 00h	/
50	Bug fix the request length is fixe	dinesha	4506d 03h	/
49	clean up	dinesha	4507d 02h	/
48	top-level cleanup	dinesha	4507d 03h	/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4507d 03h	/
46	test bench upgrade + rtl cleanup	dinesha	4509d 03h	/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4509d 08h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4511d 06h	/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4511d 07h	/