URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 79

Rev	Log message	Author	Age	Path
59	I`ve fixed some latch creation.	gabrieloshiro	5625d 03h	/
58	ALU with all opcodes ready for simulation.	gabrieloshiro	5625d 03h	/
57	A very simple testbench that checks the execution for a single instruction, i.e. no memory.	creep	5625d 03h	/
56	Several changes in the output logic to respect the pipelining.	creep	5625d 03h	/
55	ALU has all opcodes now! Comments inside ALU are completely wrong.	gabrieloshiro	5625d 04h	/
54	Processor Status register modified.	gabrieloshiro	5625d 07h	/
53	Added default header.	creep	5625d 11h	/
52	Removed unecessary always block.	creep	5626d 03h	/
51	Some first ideas on testbench.	creep	5626d 03h	/
50	Testing.	creep	5626d 05h	/