URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] - Rev 36

Rev	Log message	Author	Age	Path
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4479d 20h	/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4481d 17h	/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4482d 01h	/
13	Forgot about the new library I added	earlz	4482d 04h	/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4482d 04h	/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4485d 18h	/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4485d 18h	/
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4486d 02h	/
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4487d 01h	/
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4487d 03h	/