URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] - Rev 35

Rev	Log message	Author	Age	Path
15	MODIFIED: -- Renamed core to Wupper (vhdl files) -- Changed width of interrupt enable to number_of_interrupts	fransschreuder	3266d 21h	/
14	RENAMED: -- simulation folder	aborga	3266d 23h	/
13	RENAMED: -- script	aborga	3266d 23h	/
12	Fixed http://opencores.org/bug,view,2524	fransschreuder	3341d 23h	/
11	MODIFIED: -- updated documentation	aborga	3354d 20h	/
10	Changed: LOC => Package_pin	fransschreuder	3364d 21h	/
9	Added actual version information (Build date and svn revision) in BOARD_ID register	fransschreuder	3393d 19h	/
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3394d 01h	/
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3433d 21h	/
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3439d 19h	/