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Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 10h /
58 WISHBONE Bus update. rehayes 5267d 09h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5267d 12h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5283d 13h /
55 Minor change to instruction set details. rehayes 5283d 13h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 13h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 13h /
52 Minor changes to aide waveform debug rehayes 5283d 13h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5299d 09h /
50 incremental update to match status bit changes rehayes 5299d 10h /

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