URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 95

Rev	Log message	Author	Age	Path
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5156d 01h	/
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5161d 02h	/
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5161d 02h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5161d 02h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5162d 04h	/
70	Updated with interrupt bypass controll registers.	rehayes	5162d 04h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5162d 05h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5162d 05h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5162d 05h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5182d 01h	/