URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 63

Rev	Log message	Author	Age	Path
43	Commentary changes only, no substance.	dgisselq	2997d 17h	/
42	Minor changes.	dgisselq	2997d 17h	/
41	Bug fix. This was preventing dumpsdram from accurately reading back what had been written to the RAM earlier.	dgisselq	2997d 17h	/
40	This adds to dumpsdram the capability to run over a port, such as with busmaster_tb.	dgisselq	2999d 04h	/
39	An attempt at a bugfix. We'll see if this works any better downstream.	dgisselq	3000d 23h	/
38	Updated to remove the build dependence upon ZipCPU.	dgisselq	3001d 03h	/
37	These fixes were necessary to get the SDRAM into a working simulation capability. It is finally what it was supposed to be: cycle accurate. Sadly, to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having a problem with external input clocking in Verilator. This fixes it--but its a Verilator only change--to rtl/wbsdram.v that is.)	dgisselq	3001d 21h	/
36	A linker script, appropriate to the XuLA25-LX25 SoC.	dgisselq	3001d 23h	/
35	Updates the memory testing program to work successfully with the Gnu build tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from Binutils.	dgisselq	3001d 23h	/
34	Bug fix: This sets as a positive voltage bias (not negative) the maximum value of 0x07fff, where as the negative maximum value of 0x08000 properly (now) reflects nearly ground--as one would desire. (Last time around I had these backwards.)	dgisselq	3005d 18h	/