URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 74

Rev	Log message	Author	Age	Path
54	Updated copyright notice.	dgisselq	2925d 15h	/
53	Added a touch of error checking.	dgisselq	2965d 15h	/
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	2965d 15h	/
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	2975d 14h	/
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	2984d 16h	/
49	Added some documentation to make the read and write calls easier to understand.	dgisselq	2993d 16h	/
48	Cleaned up the documentation a touch. It no longer reads like the bugs I used to debug are still being debugged ...	dgisselq	2995d 18h	/
47	Fixes the "NAN" clocks/second output, as well as making input timing come closer to a realistic timing. (I actually don't know what timing the JTAG port is providing, but ... the new timer is closer.)	dgisselq	2995d 18h	/
46	This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v from working when long pipelined reads were interrupted by the necessity of a pair of refresh cycles.	dgisselq	2995d 18h	/
45	Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no functional difference.	dgisselq	2999d 14h	/