URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 77

Rev	Log message	Author	Age	Path
57	Fixed the TX/RX addresses so that they match the documentation: TX first, then RX.	dgisselq	2930d 12h	/
56	Brings code in line with the OpenCores core: parameterizes the reload value, and the number of bits in the timer.	dgisselq	2930d 12h	/
55	Updated copyright notice.	dgisselq	2930d 12h	/
54	Updated copyright notice.	dgisselq	2930d 12h	/
53	Added a touch of error checking.	dgisselq	2970d 12h	/
52	This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and prepares it for the 32x32 bit multiply instruction set change.	dgisselq	2970d 13h	/
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	2980d 11h	/
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	2989d 13h	/
49	Added some documentation to make the read and write calls easier to understand.	dgisselq	2998d 14h	/
48	Cleaned up the documentation a touch. It no longer reads like the bugs I used to debug are still being debugged ...	dgisselq	3000d 15h	/