URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 82

Rev	Log message	Author	Age	Path
62	Removed the pipe logic from the non-pipelined version, and made the NOOP a specific ALU instruction so that the PC is always properly updated.	dgisselq	2923d 22h	/
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	2923d 22h	/
60	LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.	dgisselq	2923d 22h	/
59	Simplified logic.	dgisselq	2923d 23h	/
58	Bug fix: the UART can now be reconfigured post-boot without a BREAK condition.	dgisselq	2923d 23h	/
57	Fixed the TX/RX addresses so that they match the documentation: TX first, then RX.	dgisselq	2931d 22h	/
56	Brings code in line with the OpenCores core: parameterizes the reload value, and the number of bits in the timer.	dgisselq	2931d 22h	/
55	Updated copyright notice.	dgisselq	2931d 22h	/
54	Updated copyright notice.	dgisselq	2931d 22h	/
53	Added a touch of error checking.	dgisselq	2971d 23h	/