URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] - Rev 91

Rev	Log message	Author	Age	Path
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2946d 14h	/
70	Cosmetic (minor) update.	dgisselq	2946d 14h	/
69	Massive logic simplification. This is also the first (verified) working version.	dgisselq	2946d 14h	/
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	2946d 14h	/
67	Simplifies logic, and guarantees that the minimum set value will always produce an int. For example, if the count was X before, setting X-1 wouldn't produce an interrupt since it had passed. Now it produces an interrupt, and keeps the next interrupt valid.	dgisselq	2946d 14h	/
66	Simplified logic (barely).	dgisselq	2946d 14h	/
65	Makes the auto-reload feature a parameterized (generic) feature, so the same code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog) timers.	dgisselq	2946d 14h	/
64	First (verified) working version.	dgisselq	2946d 14h	/
63	Simplified logic.	dgisselq	2946d 14h	/
62	Removed the pipe logic from the non-pipelined version, and made the NOOP a specific ALU instruction so that the PC is always properly updated.	dgisselq	2946d 14h	/