OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 157

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
157 change data output. simont 7729d 22h /
156 add FREQ paremeter. simont 7729d 22h /
155 add aditional tests. simont 7729d 22h /
154 File name fixed. simont 7730d 17h /
153 `ifdef added. simont 7731d 16h /
152 sub_result output added. simont 7731d 16h /
151 remove pc_r register. simont 7731d 16h /
150 fix some bugs. simont 7731d 16h /
149 pipelined acces to axternal instruction interface added. simont 7731d 16h /
148 include "8051_defines" added. simont 7731d 17h /
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7753d 17h /
146 fix bug in movc intruction. simont 7753d 17h /
145 fix bug in case of sequence of inc dptr instrucitons. simont 7758d 21h /
144 chsnge comp.des to des1 simont 7758d 21h /
143 add wire sub_result, conect it to des_acc and des1. simont 7758d 21h /
142 optimize state machine. simont 7759d 22h /
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7760d 00h /
140 cahnge assigment to pc_wait (remove istb_o) simont 7760d 00h /
139 add aditional alu destination to solve critical path. simont 7760d 18h /
138 Change buffering to save one clock per instruction. simont 7760d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.