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Rev Log message Author Age Path
53 Added GET/PUT support through a FSL bus. sybreon 6092d 15h /
52 Added log output to iverilog.log sybreon 6092d 15h /
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6093d 18h /
50 Parameterised optional components. sybreon 6093d 22h /
49 Added random seed for simulation. sybreon 6097d 01h /
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6098d 07h /
47 Added -msoft-float and -mxl-soft-div compiler flags. sybreon 6098d 07h /
46 Minor code cleanup. sybreon 6099d 03h /
45 Minor code cleanup. sybreon 6099d 04h /
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.
sybreon 6099d 17h /
43 Added interrupt simulation.
Changed "human readable" simulation output.
sybreon 6099d 17h /
42 Enable MSR_IE with software. sybreon 6099d 18h /
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
sybreon 6100d 09h /
40 Recommended to compile code with -O2/3/s sybreon 6110d 17h /
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6110d 17h /
38 Added interrupt support. sybreon 6255d 17h /
37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6269d 03h /
36 Removed asynchronous reset signal. sybreon 6269d 03h /
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6270d 00h /
34 Corrected speed issues after rev 1.9 update. sybreon 6270d 13h /

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