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Rev Log message Author Age Path
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4515d 12h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4519d 16h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4519d 16h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4519d 17h /
17 Updated reg.v content. edn_walter 4520d 10h /
16 Try to add sth. edn_walter 4524d 03h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4526d 12h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 4528d 12h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4529d 12h /
12 Added parser support for vlan tagged frames. edn_walter 4530d 10h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 4531d 12h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 4532d 12h /
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4533d 11h /
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4533d 18h /
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4533d 19h /
6 Reduced the size of the Vendor specific simulation library file. ash_riple 4535d 18h /
5 Added dcfifo to store ptp time stamps. ash_riple 4536d 10h /
4 Added source code and unit test for TSU. ash_riple 4537d 11h /
3 Added function block RTC and its unit test. ash_riple 4544d 11h /
2 Try to add sth. to the repository. ash_riple 4544d 11h /

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