URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] - Rev 49

Rev	Log message	Author	Age	Path
49	Added old uploaded documents to new repository.	root	5571d 10h	/
48	Added old uploaded documents to new repository.	root	5572d 00h	/
47	New directory structure.	root	5572d 00h	/
46	tested a new image, results are the same (i.e. works!)	jwdonal	5691d 19h	/
45	converted image to 72dpi	jwdonal	5694d 18h	/
44	converted to 72dpi	jwdonal	5694d 18h	/
43	updated for new top-level entity name	jwdonal	5694d 19h	/
42	deprecated!	jwdonal	5694d 19h	/
41	structural simulation models	jwdonal	5694d 19h	/
40	initial rev	jwdonal	5694d 19h	/
39	initial rev!	jwdonal	5694d 19h	/
38	updated for new Coregen BRAM version!	jwdonal	5694d 19h	/
37	new file to ignore!	jwdonal	5694d 23h	/
36	converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-)	jwdonal	5694d 23h	/
35	fixed spelling error	jwdonal	5694d 23h	/
34	fixed syntax	jwdonal	5694d 23h	/
33	added cvs edit feature	jwdonal	5694d 23h	/
32	initial rev	jwdonal	5694d 23h	/
31	moved to new location	jwdonal	5694d 23h	/
30	initial rev	jwdonal	5694d 23h	/