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27 Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area. mikel262 5625d 00h /
26 Added old uploaded documents to new repository. root 5632d 05h /
25 Added old uploaded documents to new repository. root 5632d 18h /
24 New directory structure. root 5632d 18h /
23 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'. 5635d 00h /
22 project released under LGPL mikel262 5635d 00h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5635d 01h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5635d 01h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6659d 21h /
18 Minor fixes. This release is FPGA proven. mikel262 6659d 21h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6681d 17h /
16 Documentation update, minor fixes mikel262 6681d 17h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6681d 19h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6685d 18h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6685d 18h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6686d 17h /
11 changed ROM memory model to synchronous mikel262 6686d 17h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles		 mikel262 6687d 19h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6690d 06h /
8 Updated DOC mikel262 6690d 06h /

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