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66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4140d 17h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4148d 09h /
64 added synthesis reports of xilinx and altera JonasDC 4148d 14h /
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4148d 14h /
62 not used anymore JonasDC 4148d 17h /
61 updated comments, added optional altera constraint JonasDC 4148d 17h /
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4151d 07h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4151d 08h /
58 made fifo full a warning JonasDC 4154d 08h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4154d 08h /
56 this is a branch to test performance of a new style of ram JonasDC 4154d 10h /
55 updated resource usage in comments JonasDC 4155d 07h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4155d 07h /
53 correctly inferred ram for altera dual port ram JonasDC 4155d 14h /
52 correct inferring of blockram, no additional resources. JonasDC 4155d 14h /
51 true dual port ram for xilinx JonasDC 4155d 15h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4155d 15h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4167d 10h /
48 Tag of the starting version of the project JonasDC 4167d 10h /
47 added documentation for the IP core. JonasDC 4235d 15h /

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