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125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7563d 20h /
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7563d 20h /
123 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7570d 21h /
122 mbist signals updated according to newest convention markom 7570d 21h /
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7627d 09h /
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7627d 09h /
119 Added support for WB B3. Some testcases were updated. tadejm 7627d 09h /
118 Some minor changes due to changes in core. tadejm 7627d 09h /
117 WB Master is now WISHBONE B3 compatible. tadejm 7627d 09h /
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7627d 09h /
115 Added signals for WB Master B3. tadejm 7627d 09h /
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7634d 12h /
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7634d 12h /
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7634d 17h /
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7634d 17h /
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7636d 16h /
109 There was missing path to hdl.var file. tadejm 7640d 13h /
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7640d 13h /
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7640d 13h /
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7645d 12h /

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