OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 48

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7993d 17h /
47 Known issues repaired mihad 7993d 23h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7998d 17h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7999d 23h /
44 Added for testing of Configuration Cycles Type 1 mihad 7999d 23h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7999d 23h /
42 Removed out of date files mihad 8012d 00h /
41 This commit was manufactured by cvs2svn to create tag 'rel_00'. 8090d 15h /
40 From these Wrod files PDF were created - added future improvements tadej 8090d 15h /
39 File not needed tadej 8090d 15h /
38 This file is not needed tadej 8090d 18h /
37 These files are not needed any more tadej 8090d 18h /
36 *** empty log message *** tadej 8090d 19h /
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8145d 02h /
34 Added missing include statements mihad 8160d 01h /
33 Added some testcases, removed un-needed fifo signals mihad 8160d 22h /
32 Added include statement that was missing and causing errors mihad 8168d 19h /
31 User defined constants used for Test Application tadej 8171d 14h /
30 Example of PCI testbench log file mihad 8171d 22h /
29 Xilinx synthesys log file tadej 8172d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.