URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 147

Rev	Log message	Author	Age	Path
147	- Updated to use current example.	cwalter	6412d 00h	/
146	- Changed to compile UART example.	cwalter	6412d 03h	/
145	- Added more VHDL files to project.	cwalter	6412d 03h	/
144	- IF stage now uses autogenerated VHDL files.	cwalter	6412d 03h	/
143	- Added more complex UART example.	cwalter	6412d 03h	/
142	- Added gap between characters sent and changed last character to CR.	cwalter	6412d 03h	/
141	- Added delay between characters.	cwalter	6412d 03h	/
140	- Test bench for RISE with UART.	cwalter	6412d 03h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6412d 04h	/
138	- Fixed binary to VHDL converter.	cwalter	6412d 04h	/
137	- Added binary to VHDL converter.	cwalter	6412d 05h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6412d 05h	/
135	uart_address_0 was a latch -> changed	ustadler	6413d 01h	/
134	Added second test program for testing uart.	jlechner	6413d 01h	/
133	- Fixed bug with ST opcodes.	cwalter	6413d 03h	/
132	Added test program for testing uart.	jlechner	6413d 03h	/
131	Changed high active resets to low active ones.	jlechner	6413d 03h	/
130	Removed obsolete line	jlechner	6413d 03h	/
129	Sample assembler program for accessing uart	jlechner	6413d 03h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6413d 03h	/