URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 288

Rev	Log message	Author	Age	Path
288	updates for release 1.1	arniml	5895d 13h	/
287	add notes on FPGA implementation	arniml	5895d 13h	/
286	hierarchy update, RAM and ROM clarification	arniml	5895d 13h	/
285	generate D for synchronous implementation in clocked process	arniml	5896d 14h	/
284	better support for ISE/XST: opc_table and opc_decoder merged into decoder_pack and decoder	arniml	5896d 14h	/
283	update to new mnemonic decoder	arniml	5896d 14h	/
282	decouple bidir port T0 from P1 fixes testcase black_box/tx/t0	arniml	5897d 14h	/
281	clarify testcase compilation	arniml	5897d 14h	/
280	added syn directory structure	arniml	5898d 13h	/
279	update	arniml	5913d 12h	/
278	initial check-in	arniml	5913d 14h	/
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6394d 12h	/
276	add change notes for release 1.0	arniml	6394d 12h	/
275	fix sensitivity list	arniml	6395d 10h	/
274	revision 1.0	arniml	6395d 11h	/
273	reset counter_q	arniml	6412d 21h	/
272	fix entity port names	arniml	6416d 23h	/
271	initial check-in	arniml	6416d 23h	/
270	fix component name	arniml	6417d 00h	/
269	update list for inclusion of t8243 testbenches	arniml	6544d 12h	/