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45 Added slave address configurability rherveille 7582d 00h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7667d 02h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7667d 02h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7677d 00h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7677d 00h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7677d 00h /.
39 Forgot an 'end if' :-/ rherveille 7696d 20h /.
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7700d 04h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7736d 19h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7851d 20h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7885d 11h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7889d 09h /.
33 Fixed a bug in the Command Register declaration. rherveille 7911d 18h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7921d 17h /.
31 Core is now a Multimaster I2C controller. rherveille 7925d 19h /.
30 Small code simplifications rherveille 7925d 19h /.
29 Core is now a Multimaster I2C controller rherveille 7925d 20h /.
28 *** empty log message *** rherveille 7951d 12h /.
27 Cleaned up code rherveille 7951d 12h /.
26 *** empty log message *** rherveille 7954d 20h /.

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