URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 134

Rev	Log message	Author	Age	Path
134	fix bug in case execution of two data dependent instructions.	simont	7761d 12h	/8051/tags/rel_1
133	fix bug in substraction.	simont	7761d 15h	/8051/tags/rel_1
132	change branch instruction execution (reduse needed clock periods).	simont	7765d 06h	/8051/tags/rel_1
131	prepare programs for new timing.	simont	7765d 07h	/8051/tags/rel_1
130	prepared programs for new timing.	simont	7765d 07h	/8051/tags/rel_1
129	updated...	simont	7765d 07h	/8051/tags/rel_1
128	chance idat_ir to 24 bit wide	simont	7774d 14h	/8051/tags/rel_1
127	fix bug (cyc_o and stb_o)	simont	7774d 14h	/8051/tags/rel_1
126	define OC8051_XILINX_RAMB added	simont	7774d 14h	/8051/tags/rel_1
125	update, add prescaler, rclk, tclk.	simont	7774d 14h	/8051/tags/rel_1
124	add support for external rom from xilinx ramb4	simont	7774d 14h	/8051/tags/rel_1
123	fiz bug iv pcs operation.	simont	7776d 09h	/8051/tags/rel_1
122	deifne OC8051_ROM added	simont	7779d 14h	/8051/tags/rel_1
121	Change pc add value from 23'h to 16'h	simont	7779d 14h	/8051/tags/rel_1
120	defines for pherypherals added	simont	7780d 11h	/8051/tags/rel_1
119	remove signal sbuf_txd [12:11]	simont	7780d 15h	/8051/tags/rel_1
118	change wr_sft to 2 bit wire.	simont	7781d 07h	/8051/tags/rel_1
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7781d 08h	/8051/tags/rel_1
116	change sfr's interface.	simont	7783d 09h	/8051/tags/rel_1
115	change uart to meet timing.	simont	7783d 10h	/8051/tags/rel_1