URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 185

Rev	Log message	Author	Age	Path
185		root	5588d 15h	/8051/tags/rel_1
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7717d 13h	/8051/tags/rel_1
146	fix bug in movc intruction.	simont	7717d 13h	/8051/tags/rel_1
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7722d 17h	/8051/tags/rel_1
144	chsnge comp.des to des1	simont	7722d 17h	/8051/tags/rel_1
143	add wire sub_result, conect it to des_acc and des1.	simont	7722d 17h	/8051/tags/rel_1
142	optimize state machine.	simont	7723d 18h	/8051/tags/rel_1
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7723d 20h	/8051/tags/rel_1
140	cahnge assigment to pc_wait (remove istb_o)	simont	7723d 20h	/8051/tags/rel_1
139	add aditional alu destination to solve critical path.	simont	7724d 13h	/8051/tags/rel_1
138	Change buffering to save one clock per instruction.	simont	7724d 13h	/8051/tags/rel_1
137	change to fit xrom.	simont	7724d 19h	/8051/tags/rel_1
136	registering outputs.	simont	7724d 19h	/8051/tags/rel_1
135	prepared start of receiving if ren is not active.	simont	7730d 18h	/8051/tags/rel_1
134	fix bug in case execution of two data dependent instructions.	simont	7730d 18h	/8051/tags/rel_1
133	fix bug in substraction.	simont	7730d 21h	/8051/tags/rel_1
132	change branch instruction execution (reduse needed clock periods).	simont	7734d 12h	/8051/tags/rel_1
131	prepare programs for new timing.	simont	7734d 12h	/8051/tags/rel_1
130	prepared programs for new timing.	simont	7734d 12h	/8051/tags/rel_1
129	updated...	simont	7734d 12h	/8051/tags/rel_1