URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl] - Rev 90

Rev	Log message	Author	Age	Path
90	change module name.	simont	7813d 17h	/8051/tags/rel_1/rtl
89	Replaced oc8051_ram by generic_dpram.	rherveille	7874d 20h	/8051/tags/rel_1/rtl
88	fix bugs	simont	7879d 21h	/8051/tags/rel_1/rtl
87	add include oc8051_defines.v	simont	7879d 21h	/8051/tags/rel_1/rtl
82	replace some modules	simont	7887d 20h	/8051/tags/rel_1/rtl
81	initial import	simont	7887d 20h	/8051/tags/rel_1/rtl
80	removing unused modules	simont	7887d 21h	/8051/tags/rel_1/rtl
78	alu with registered outputs	simont	7947d 20h	/8051/tags/rel_1/rtl
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7956d 17h	/8051/tags/rel_1/rtl
76	add module oc8051_sfr, 256 bytes internal ram	simont	7956d 17h	/8051/tags/rel_1/rtl
75	initial import	simont	7956d 17h	/8051/tags/rel_1/rtl
73	initial import	simont	7964d 18h	/8051/tags/rel_1/rtl
72	fix bug in interface to external data ram	simont	7964d 20h	/8051/tags/rel_1/rtl
67	add parameters for instruction cache	simont	7968d 21h	/8051/tags/rel_1/rtl
62	fix bugs in instruction interface	simont	7969d 18h	/8051/tags/rel_1/rtl
54	cahnge interface to instruction rom	simont	7975d 16h	/8051/tags/rel_1/rtl
47	remove unused files	simont	7992d 17h	/8051/tags/rel_1/rtl
46	prepared header	simont	7992d 17h	/8051/tags/rel_1/rtl
45	prepared header	simont	7992d 17h	/8051/tags/rel_1/rtl
44	prepared header	simont	7992d 18h	/8051/tags/rel_1/rtl