URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] - Rev 135

Rev	Log message	Author	Age	Path
135	prepared start of receiving if ren is not active.	simont	7773d 22h	/8051/tags/rel_12
134	fix bug in case execution of two data dependent instructions.	simont	7773d 22h	/8051/tags/rel_12
133	fix bug in substraction.	simont	7774d 01h	/8051/tags/rel_12
132	change branch instruction execution (reduse needed clock periods).	simont	7777d 16h	/8051/tags/rel_12
131	prepare programs for new timing.	simont	7777d 16h	/8051/tags/rel_12
130	prepared programs for new timing.	simont	7777d 16h	/8051/tags/rel_12
129	updated...	simont	7777d 16h	/8051/tags/rel_12
128	chance idat_ir to 24 bit wide	simont	7786d 23h	/8051/tags/rel_12
127	fix bug (cyc_o and stb_o)	simont	7786d 23h	/8051/tags/rel_12
126	define OC8051_XILINX_RAMB added	simont	7786d 23h	/8051/tags/rel_12
125	update, add prescaler, rclk, tclk.	simont	7786d 23h	/8051/tags/rel_12
124	add support for external rom from xilinx ramb4	simont	7786d 23h	/8051/tags/rel_12
123	fiz bug iv pcs operation.	simont	7788d 19h	/8051/tags/rel_12
122	deifne OC8051_ROM added	simont	7791d 23h	/8051/tags/rel_12
121	Change pc add value from 23'h to 16'h	simont	7791d 23h	/8051/tags/rel_12
120	defines for pherypherals added	simont	7792d 21h	/8051/tags/rel_12
119	remove signal sbuf_txd [12:11]	simont	7793d 00h	/8051/tags/rel_12
118	change wr_sft to 2 bit wire.	simont	7793d 17h	/8051/tags/rel_12
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7793d 18h	/8051/tags/rel_12
116	change sfr's interface.	simont	7795d 18h	/8051/tags/rel_12