URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 181

Rev	Log message	Author	Age	Path
181	Simulation reports added.	simont	7678d 10h	/8051/tags/rel_12/rtl
179	add /* synopsys xx_case */ to case statments.	simont	7678d 11h	/8051/tags/rel_12/rtl
178	x replaced with 0.	simont	7678d 13h	/8051/tags/rel_12/rtl
177	Fix bug in case of writing and reading from same address.	simont	7689d 16h	/8051/tags/rel_12/rtl
175	initial inport.	simont	7689d 18h	/8051/tags/rel_12/rtl
174	ram modules added.	simont	7689d 18h	/8051/tags/rel_12/rtl
173	simualtion `ifdef added	simont	7689d 18h	/8051/tags/rel_12/rtl
172	BIST signals added.	simont	7692d 18h	/8051/tags/rel_12/rtl
171	fix bug in DA operation.	simont	7700d 15h	/8051/tags/rel_12/rtl
158	fix bug.	simont	7704d 21h	/8051/tags/rel_12/rtl
153	`ifdef added.	simont	7706d 15h	/8051/tags/rel_12/rtl
152	sub_result output added.	simont	7706d 15h	/8051/tags/rel_12/rtl
151	remove pc_r register.	simont	7706d 15h	/8051/tags/rel_12/rtl
150	fix some bugs.	simont	7706d 15h	/8051/tags/rel_12/rtl
149	pipelined acces to axternal instruction interface added.	simont	7706d 15h	/8051/tags/rel_12/rtl
148	include "8051_defines" added.	simont	7706d 15h	/8051/tags/rel_12/rtl
146	fix bug in movc intruction.	simont	7728d 15h	/8051/tags/rel_12/rtl
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7733d 19h	/8051/tags/rel_12/rtl
144	chsnge comp.des to des1	simont	7733d 19h	/8051/tags/rel_12/rtl
143	add wire sub_result, conect it to des_acc and des1.	simont	7733d 19h	/8051/tags/rel_12/rtl