URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 158

Rev	Log message	Author	Age	Path
158	fix bug.	simont	7695d 14h	/8051/tags/rel_2
157	change data output.	simont	7695d 14h	/8051/tags/rel_2
156	add FREQ paremeter.	simont	7695d 14h	/8051/tags/rel_2
155	add aditional tests.	simont	7695d 14h	/8051/tags/rel_2
154	File name fixed.	simont	7696d 08h	/8051/tags/rel_2
153	`ifdef added.	simont	7697d 08h	/8051/tags/rel_2
152	sub_result output added.	simont	7697d 08h	/8051/tags/rel_2
151	remove pc_r register.	simont	7697d 08h	/8051/tags/rel_2
150	fix some bugs.	simont	7697d 08h	/8051/tags/rel_2
149	pipelined acces to axternal instruction interface added.	simont	7697d 08h	/8051/tags/rel_2
148	include "8051_defines" added.	simont	7697d 08h	/8051/tags/rel_2
146	fix bug in movc intruction.	simont	7719d 09h	/8051/tags/rel_2
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7724d 12h	/8051/tags/rel_2
144	chsnge comp.des to des1	simont	7724d 12h	/8051/tags/rel_2
143	add wire sub_result, conect it to des_acc and des1.	simont	7724d 12h	/8051/tags/rel_2
142	optimize state machine.	simont	7725d 14h	/8051/tags/rel_2
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7725d 15h	/8051/tags/rel_2
140	cahnge assigment to pc_wait (remove istb_o)	simont	7725d 15h	/8051/tags/rel_2
139	add aditional alu destination to solve critical path.	simont	7726d 09h	/8051/tags/rel_2
138	Change buffering to save one clock per instruction.	simont	7726d 09h	/8051/tags/rel_2