URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 81

Rev	Log message	Author	Age	Path
81	initial import	simont	7853d 05h	/8051/tags/rel_2/rtl
80	removing unused modules	simont	7853d 05h	/8051/tags/rel_2/rtl
78	alu with registered outputs	simont	7913d 05h	/8051/tags/rel_2/rtl
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7922d 02h	/8051/tags/rel_2/rtl
76	add module oc8051_sfr, 256 bytes internal ram	simont	7922d 02h	/8051/tags/rel_2/rtl
75	initial import	simont	7922d 02h	/8051/tags/rel_2/rtl
73	initial import	simont	7930d 03h	/8051/tags/rel_2/rtl
72	fix bug in interface to external data ram	simont	7930d 05h	/8051/tags/rel_2/rtl
67	add parameters for instruction cache	simont	7934d 06h	/8051/tags/rel_2/rtl
62	fix bugs in instruction interface	simont	7935d 03h	/8051/tags/rel_2/rtl
54	cahnge interface to instruction rom	simont	7941d 01h	/8051/tags/rel_2/rtl
47	remove unused files	simont	7958d 02h	/8051/tags/rel_2/rtl
46	prepared header	simont	7958d 02h	/8051/tags/rel_2/rtl
45	prepared header	simont	7958d 02h	/8051/tags/rel_2/rtl
44	prepared header	simont	7958d 03h	/8051/tags/rel_2/rtl
41	remove unused files	simont	7958d 04h	/8051/tags/rel_2/rtl
40	added sigals for interacting with external ram	simont	7978d 06h	/8051/tags/rel_2/rtl
38	fix some bugs	simont	7985d 04h	/8051/tags/rel_2/rtl
37	added signals ack, stb and cyc	simont	7985d 04h	/8051/tags/rel_2/rtl
36	fix bugs in mode 0	simont	7985d 04h	/8051/tags/rel_2/rtl