URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] - Rev 166

Rev	Log message	Author	Age	Path
166	Change test monitor from ports to external data memory.	simont	7706d 18h	/8051/trunk/bench
165	remove dumpvars.	simont	7706d 22h	/8051/trunk/bench
164	initial inport.	simont	7706d 23h	/8051/trunk/bench
163	initial inport	simont	7706d 23h	/8051/trunk/bench
157	change data output.	simont	7707d 00h	/8051/trunk/bench
156	add FREQ paremeter.	simont	7707d 00h	/8051/trunk/bench
155	add aditional tests.	simont	7707d 00h	/8051/trunk/bench
130	prepared programs for new timing.	simont	7747d 18h	/8051/trunk/bench
129	updated...	simont	7747d 18h	/8051/trunk/bench
125	update, add prescaler, rclk, tclk.	simont	7757d 01h	/8051/trunk/bench
124	add support for external rom from xilinx ramb4	simont	7757d 01h	/8051/trunk/bench
120	defines for pherypherals added	simont	7762d 22h	/8051/trunk/bench
111	Remove instruction cache and wb_interface	simont	7769d 15h	/8051/trunk/bench
103	rename signals	simont	7770d 20h	/8051/trunk/bench
97	initial inport	simont	7770d 23h	/8051/trunk/bench
96	initial import	simont	7770d 23h	/8051/trunk/bench
84	remove wb_bus_mon	simont	7849d 20h	/8051/trunk/bench
74	add module oc8051_wb_iinterface	simont	7926d 18h	/8051/trunk/bench
68	add instruction cache and DELAY parameters for external ram, rom	simont	7930d 21h	/8051/trunk/bench
59	add external rom	simont	7937d 16h	/8051/trunk/bench