URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 179

Rev	Log message	Author	Age	Path
179	add /* synopsys xx_case */ to case statments.	simont	7680d 22h	/8051/trunk/rtl/verilog
178	x replaced with 0.	simont	7681d 00h	/8051/trunk/rtl/verilog
177	Fix bug in case of writing and reading from same address.	simont	7692d 03h	/8051/trunk/rtl/verilog
175	initial inport.	simont	7692d 05h	/8051/trunk/rtl/verilog
174	ram modules added.	simont	7692d 05h	/8051/trunk/rtl/verilog
173	simualtion `ifdef added	simont	7692d 05h	/8051/trunk/rtl/verilog
172	BIST signals added.	simont	7695d 05h	/8051/trunk/rtl/verilog
171	fix bug in DA operation.	simont	7703d 02h	/8051/trunk/rtl/verilog
158	fix bug.	simont	7707d 08h	/8051/trunk/rtl/verilog
153	`ifdef added.	simont	7709d 02h	/8051/trunk/rtl/verilog
152	sub_result output added.	simont	7709d 02h	/8051/trunk/rtl/verilog
151	remove pc_r register.	simont	7709d 02h	/8051/trunk/rtl/verilog
150	fix some bugs.	simont	7709d 02h	/8051/trunk/rtl/verilog
149	pipelined acces to axternal instruction interface added.	simont	7709d 02h	/8051/trunk/rtl/verilog
148	include "8051_defines" added.	simont	7709d 02h	/8051/trunk/rtl/verilog
146	fix bug in movc intruction.	simont	7731d 02h	/8051/trunk/rtl/verilog
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7736d 06h	/8051/trunk/rtl/verilog
144	chsnge comp.des to des1	simont	7736d 06h	/8051/trunk/rtl/verilog
143	add wire sub_result, conect it to des_acc and des1.	simont	7736d 06h	/8051/trunk/rtl/verilog
142	optimize state machine.	simont	7737d 08h	/8051/trunk/rtl/verilog