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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 157

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Rev Log message Author Age Path
157 Added interrupt capability. sybreon 6014d 21h /aemb/trunk/rtl/verilog
150 Optimisations. sybreon 6017d 21h /aemb/trunk/rtl/verilog
149 Minor performance optimisation. sybreon 6018d 05h /aemb/trunk/rtl/verilog
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 6018d 10h /aemb/trunk/rtl/verilog
147 Disconnect from pipeline. sybreon 6018d 13h /aemb/trunk/rtl/verilog
140 Fixed minor typos. sybreon 6018d 14h /aemb/trunk/rtl/verilog
134 Minor performance improvements. sybreon 6019d 12h /aemb/trunk/rtl/verilog
132 Fixed minor typos. sybreon 6020d 05h /aemb/trunk/rtl/verilog
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 6020d 05h /aemb/trunk/rtl/verilog
127 Fixed pipelined latching of data bug. sybreon 6022d 15h /aemb/trunk/rtl/verilog
126 Fixed CMP bug. sybreon 6022d 15h /aemb/trunk/rtl/verilog
125 Passes arithmetic tests with single thread. sybreon 6024d 18h /aemb/trunk/rtl/verilog
124 FASM removed. sybreon 6024d 18h /aemb/trunk/rtl/verilog
120 Basic version with some features left out. sybreon 6025d 13h /aemb/trunk/rtl/verilog
119 Initial import. sybreon 6025d 13h /aemb/trunk/rtl/verilog
118 Initial import. sybreon 6028d 05h /aemb/trunk/rtl/verilog
114 changed MSR bits sybreon 6034d 14h /aemb/trunk/rtl/verilog
105 Patch interrupt bug. sybreon 6116d 05h /aemb/trunk/rtl/verilog
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6117d 14h /aemb/trunk/rtl/verilog
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6117d 14h /aemb/trunk/rtl/verilog

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