OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 204

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
204 added initial exception handler in the pipeline. sybreon 5468d 07h /aemb/trunk/rtl/verilog
203 optimised exception signals. sybreon 5468d 07h /aemb/trunk/rtl/verilog
202 added basic exception signals. sybreon 5468d 07h /aemb/trunk/rtl/verilog
191 New directory structure. root 5598d 10h /aemb/trunk/rtl/verilog
190 Housekeeping. sybreon 5612d 20h /aemb/trunk/rtl/verilog
189 *** empty log message *** sybreon 5820d 19h /aemb/trunk/rtl/verilog
188 *** empty log message *** sybreon 5820d 20h /aemb/trunk/rtl/verilog
187 nc sybreon 5835d 07h /aemb/trunk/rtl/verilog
186 added tool specific conditional defines. sybreon 5835d 07h /aemb/trunk/rtl/verilog
172 single thread design sybreon 5874d 19h /aemb/trunk/rtl/verilog
171 *** empty log message *** sybreon 5875d 07h /aemb/trunk/rtl/verilog
170 initial sybreon 5875d 07h /aemb/trunk/rtl/verilog
169 *** empty log message *** sybreon 5875d 07h /aemb/trunk/rtl/verilog
168 *** empty log message *** sybreon 5875d 07h /aemb/trunk/rtl/verilog
167 *** empty log message *** sybreon 5875d 08h /aemb/trunk/rtl/verilog
166 final upload sybreon 5875d 08h /aemb/trunk/rtl/verilog
160 minor typo. sybreon 5900d 15h /aemb/trunk/rtl/verilog
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.
sybreon 5900d 15h /aemb/trunk/rtl/verilog
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.
sybreon 5910d 16h /aemb/trunk/rtl/verilog
157 Added interrupt capability. sybreon 5910d 20h /aemb/trunk/rtl/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.