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[/] [aemb/] [trunk/] [sim/] - Rev 79

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Rev Log message Author Age Path
79 Modified for AEMB2 sybreon 6060d 04h /aemb/trunk/sim
73 Moved simulation kernel into code. sybreon 6070d 11h /aemb/trunk/sim
71 Old version deprecated. sybreon 6077d 14h /aemb/trunk/sim
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6080d 10h /aemb/trunk/sim
67 Minor simulation fixes. sybreon 6082d 09h /aemb/trunk/sim
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6086d 06h /aemb/trunk/sim
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6087d 05h /aemb/trunk/sim
53 Added GET/PUT support through a FSL bus. sybreon 6091d 08h /aemb/trunk/sim
52 Added log output to iverilog.log sybreon 6091d 08h /aemb/trunk/sim
50 Parameterised optional components. sybreon 6092d 14h /aemb/trunk/sim
49 Added random seed for simulation. sybreon 6095d 18h /aemb/trunk/sim
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6098d 09h /aemb/trunk/sim
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6099d 01h /aemb/trunk/sim
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6109d 09h /aemb/trunk/sim
38 Added interrupt support. sybreon 6254d 10h /aemb/trunk/sim
31 Removed byte acrobatics. sybreon 6284d 13h /aemb/trunk/sim
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6287d 13h /aemb/trunk/sim
22 Added support for 8-bit and 16-bit data types. sybreon 6289d 06h /aemb/trunk/sim
19 Added initial unified memory core. sybreon 6301d 15h /aemb/trunk/sim
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6302d 08h /aemb/trunk/sim

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