URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_16/] - Rev 163

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5589d 13h	/can/tags/rel_16
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7609d 01h	/tags/rel_16
118	Artisan RAM fixed (when not using BIST).	mohor	7617d 22h	/trunk
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7617d 22h	/trunk
115	Artisan ram instances added.	simons	7623d 16h	/trunk
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7650d 17h	/trunk
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7652d 17h	/trunk
110	Fixed according to the linter.	mohor	7652d 17h	/trunk
109	Fixed according to the linter.	mohor	7652d 18h	/trunk
108	Fixed according to the linter.	mohor	7652d 19h	/trunk
107	Fixed according to the linter.	mohor	7652d 19h	/trunk
106	Unused signal removed.	mohor	7658d 17h	/trunk
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7659d 06h	/trunk
102	Little fixes (to fix warnings).	mohor	7661d 21h	/trunk
100	Synchronization changed.	mohor	7665d 23h	/trunk
99	PCI_BIST replaced with CAN_BIST.	mohor	7665d 23h	/trunk
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7671d 10h	/trunk
95	Virtual silicon ram instances added.	simons	7671d 11h	/trunk
93	synthesis full_case parallel_case fixed.	mohor	7676d 23h	/trunk
92	clkout is clk/2 after the reset.	mohor	7677d 07h	/trunk