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Rev Log message Author Age Path
161 New directory structure. root 5614d 11h /can/tags/rel_18
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7601d 10h /tags/rel_18
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7601d 10h /trunk
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7602d 06h /trunk
125 Synchronization changed, error counters fixed. mohor 7606d 12h /trunk
124 ALTERA_RAM supported. mohor 7626d 18h /trunk
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7634d 00h /trunk
119 Artisan RAMs added. mohor 7642d 21h /trunk
118 Artisan RAM fixed (when not using BIST). mohor 7642d 21h /trunk
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7642d 21h /trunk
115 Artisan ram instances added. simons 7648d 15h /trunk
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7675d 16h /trunk
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7677d 16h /trunk
110 Fixed according to the linter. mohor 7677d 16h /trunk
109 Fixed according to the linter. mohor 7677d 17h /trunk
108 Fixed according to the linter. mohor 7677d 17h /trunk
107 Fixed according to the linter. mohor 7677d 18h /trunk
106 Unused signal removed. mohor 7683d 16h /trunk
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7684d 05h /trunk
102 Little fixes (to fix warnings). mohor 7686d 20h /trunk

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