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Rev Log message Author Age Path
161 New directory structure. root 5623d 03h /can/tags/rel_20
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7385d 07h /tags/rel_20
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7385d 07h /trunk
140 I forgot to thange one signal name. igorm 7440d 05h /trunk
139 Signal bus_off_on added. igorm 7440d 06h /trunk
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7479d 08h /trunk
137 Header changed. mohor 7479d 09h /trunk
136 Error counters changed. mohor 7479d 09h /trunk
135 Header changed. mohor 7479d 09h /trunk
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7587d 06h /trunk
130 mbist signals updated according to newest convention markom 7593d 17h /trunk
129 Error counters changed. mohor 7610d 02h /trunk
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7610d 02h /trunk
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7610d 22h /trunk
125 Synchronization changed, error counters fixed. mohor 7615d 04h /trunk
124 ALTERA_RAM supported. mohor 7635d 10h /trunk
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7642d 16h /trunk
119 Artisan RAMs added. mohor 7651d 13h /trunk
118 Artisan RAM fixed (when not using BIST). mohor 7651d 13h /trunk
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7651d 13h /trunk

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