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[/] [can/] [tags/] [rel_22/] [rtl/] - Rev 163

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Rev Log message Author Age Path
161 New directory structure. root 5589d 11h /can/tags/rel_22/rtl
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7186d 00h /can/tags/rel_22/rtl
145 Arbitration bug fixed. igorm 7186d 00h /can/tags/rel_22/rtl
143 Bit acceptance_filter_mode was inverted. igorm 7332d 16h /can/tags/rel_22/rtl
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7351d 15h /can/tags/rel_22/rtl
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7445d 16h /can/tags/rel_22/rtl
137 Header changed. mohor 7445d 16h /can/tags/rel_22/rtl
136 Error counters changed. mohor 7445d 17h /can/tags/rel_22/rtl
135 Header changed. mohor 7445d 17h /can/tags/rel_22/rtl
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7553d 14h /can/tags/rel_22/rtl
130 mbist signals updated according to newest convention markom 7560d 01h /can/tags/rel_22/rtl
129 Error counters changed. mohor 7576d 10h /can/tags/rel_22/rtl
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7577d 06h /can/tags/rel_22/rtl
125 Synchronization changed, error counters fixed. mohor 7581d 12h /can/tags/rel_22/rtl
124 ALTERA_RAM supported. mohor 7601d 18h /can/tags/rel_22/rtl
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7609d 00h /can/tags/rel_22/rtl
118 Artisan RAM fixed (when not using BIST). mohor 7617d 21h /can/tags/rel_22/rtl
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7617d 21h /can/tags/rel_22/rtl
115 Artisan ram instances added. simons 7623d 15h /can/tags/rel_22/rtl
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7650d 16h /can/tags/rel_22/rtl

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