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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 31

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Rev	Log message	Author	Age	Path
31	Wishbone interface added.	mohor	7823d 23h	/can/tags/rel_9/bench/verilog/can_testbench.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7825d 06h	/can/tags/rel_9/bench/verilog/can_testbench.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7825d 22h	/can/tags/rel_9/bench/verilog/can_testbench.v
26	Backup.	mohor	7830d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
25	* empty log message *	mohor	7830d 10h	/can/tags/rel_9/bench/verilog/can_testbench.v
24	backup.	mohor	7834d 23h	/can/tags/rel_9/bench/verilog/can_testbench.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7849d 11h	/can/tags/rel_9/bench/verilog/can_testbench.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7850d 03h	/can/tags/rel_9/bench/verilog/can_testbench.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7850d 10h	/can/tags/rel_9/bench/verilog/can_testbench.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7850d 11h	/can/tags/rel_9/bench/verilog/can_testbench.v
17	Addresses corrected to decimal values (previously hex).	mohor	7851d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
16	rx_fifo is now working.	mohor	7851d 12h	/can/tags/rel_9/bench/verilog/can_testbench.v
15	Temporary version (backup).	mohor	7855d 06h	/can/tags/rel_9/bench/verilog/can_testbench.v
14	rx fifo added. Not 100 % verified, yet.	mohor	7856d 02h	/can/tags/rel_9/bench/verilog/can_testbench.v
11	Acceptance filter added.	mohor	7857d 22h	/can/tags/rel_9/bench/verilog/can_testbench.v
10	Backup version.	mohor	7868d 20h	/can/tags/rel_9/bench/verilog/can_testbench.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7870d 00h	/can/tags/rel_9/bench/verilog/can_testbench.v
8	Testbench define file added. Clock divider register added.	mohor	7870d 08h	/can/tags/rel_9/bench/verilog/can_testbench.v
7	Tripple sampling supported.	mohor	7870d 23h	/can/tags/rel_9/bench/verilog/can_testbench.v
6	Commented lines removed.	mohor	7871d 01h	/can/tags/rel_9/bench/verilog/can_testbench.v

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 31

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