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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 61

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Rev	Log message	Author	Age	Path
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7794d 16h	/can/tags/rel_9/bench/verilog/can_testbench.v
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7794d 17h	/can/tags/rel_9/bench/verilog/can_testbench.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7794d 17h	/can/tags/rel_9/bench/verilog/can_testbench.v
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7801d 06h	/can/tags/rel_9/bench/verilog/can_testbench.v
50	Top level signal names changed.	mohor	7801d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
48	Actel APA ram supported.	mohor	7804d 23h	/can/tags/rel_9/bench/verilog/can_testbench.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7815d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
38	Temporary backup version (still fully operable).	mohor	7816d 21h	/can/tags/rel_9/bench/verilog/can_testbench.v
35	Several registers added. Not finished, yet.	mohor	7820d 01h	/can/tags/rel_9/bench/verilog/can_testbench.v
34	Errors monitoring improved. arbitration_lost improved.	mohor	7822d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
31	Wishbone interface added.	mohor	7823d 21h	/can/tags/rel_9/bench/verilog/can_testbench.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7825d 03h	/can/tags/rel_9/bench/verilog/can_testbench.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7825d 19h	/can/tags/rel_9/bench/verilog/can_testbench.v
26	Backup.	mohor	7830d 04h	/can/tags/rel_9/bench/verilog/can_testbench.v
25	* empty log message *	mohor	7830d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
24	backup.	mohor	7834d 20h	/can/tags/rel_9/bench/verilog/can_testbench.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7849d 08h	/can/tags/rel_9/bench/verilog/can_testbench.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7850d 00h	/can/tags/rel_9/bench/verilog/can_testbench.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7850d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7850d 08h	/can/tags/rel_9/bench/verilog/can_testbench.v

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 61

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