OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] - Rev 121

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7585d 18h /can/trunk
119 Artisan RAMs added. mohor 7594d 15h /can/trunk
118 Artisan RAM fixed (when not using BIST). mohor 7594d 15h /can/trunk
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7594d 15h /can/trunk
115 Artisan ram instances added. simons 7600d 09h /can/trunk
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7627d 09h /can/trunk
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7629d 10h /can/trunk
110 Fixed according to the linter. mohor 7629d 10h /can/trunk
109 Fixed according to the linter. mohor 7629d 11h /can/trunk
108 Fixed according to the linter. mohor 7629d 11h /can/trunk
107 Fixed according to the linter. mohor 7629d 12h /can/trunk
106 Unused signal removed. mohor 7635d 09h /can/trunk
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7635d 23h /can/trunk
102 Little fixes (to fix warnings). mohor 7638d 14h /can/trunk
100 Synchronization changed. mohor 7642d 15h /can/trunk
99 PCI_BIST replaced with CAN_BIST. mohor 7642d 15h /can/trunk
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7648d 03h /can/trunk
95 Virtual silicon ram instances added. simons 7648d 04h /can/trunk
93 synthesis full_case parallel_case fixed. mohor 7653d 15h /can/trunk
92 clkout is clk/2 after the reset. mohor 7653d 23h /can/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.