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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] - Rev 96

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Rev Log message Author Age Path
96 Working. mohor 7483d 19h /dbg_interface/tags/highland_ver1/bench
95 Temp version. mohor 7484d 07h /dbg_interface/tags/highland_ver1/bench
93 tmp version. mohor 7485d 18h /dbg_interface/tags/highland_ver1/bench
92 temp version. mohor 7488d 22h /dbg_interface/tags/highland_ver1/bench
91 tmp version. mohor 7489d 17h /dbg_interface/tags/highland_ver1/bench
90 tmp version. mohor 7490d 12h /dbg_interface/tags/highland_ver1/bench
89 temp4 version. mohor 7491d 18h /dbg_interface/tags/highland_ver1/bench
88 temp3 version. mohor 7492d 12h /dbg_interface/tags/highland_ver1/bench
87 tmp2 version. mohor 7493d 17h /dbg_interface/tags/highland_ver1/bench
80 New version of the debug interface. Not finished, yet. mohor 7506d 15h /dbg_interface/tags/highland_ver1/bench
75 Simulation files. mohor 7567d 13h /dbg_interface/tags/highland_ver1/bench
73 CRC logic changed. mohor 7567d 13h /dbg_interface/tags/highland_ver1/bench
63 Three more chains added for cpu debug access. simons 7623d 16h /dbg_interface/tags/highland_ver1/bench
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 15h /dbg_interface/tags/highland_ver1/bench
38 Few outputs for boundary scan chain added. mohor 8157d 15h /dbg_interface/tags/highland_ver1/bench
36 Structure changed. Hooks for jtag chain added. mohor 8161d 14h /dbg_interface/tags/highland_ver1/bench
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8301d 18h /dbg_interface/tags/highland_ver1/bench
15 bs_chain_o added. mohor 8303d 19h /dbg_interface/tags/highland_ver1/bench
13 Signal names changed to lowercase. mohor 8304d 19h /dbg_interface/tags/highland_ver1/bench
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8305d 20h /dbg_interface/tags/highland_ver1/bench

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