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[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 45

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Rev	Log message	Author	Age	Path
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8151d 20h	/dbg_interface/tags/rel_1/rtl/verilog
44	Signal names changed to lower case.	mohor	8151d 20h	/dbg_interface/tags/rel_1/rtl/verilog
43	Intentional error removed.	mohor	8156d 19h	/dbg_interface/tags/rel_1/rtl/verilog
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8156d 21h	/dbg_interface/tags/rel_1/rtl/verilog
41	Function changed to logic because of some synthesis warnings.	mohor	8164d 18h	/dbg_interface/tags/rel_1/rtl/verilog
40	Signal tdo_padoe_o changed back to tdo_padoen_o.	mohor	8178d 18h	/dbg_interface/tags/rel_1/rtl/verilog
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8179d 19h	/dbg_interface/tags/rel_1/rtl/verilog
38	Few outputs for boundary scan chain added.	mohor	8192d 18h	/dbg_interface/tags/rel_1/rtl/verilog
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8192d 22h	/dbg_interface/tags/rel_1/rtl/verilog
36	Structure changed. Hooks for jtag chain added.	mohor	8196d 17h	/dbg_interface/tags/rel_1/rtl/verilog
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8226d 20h	/dbg_interface/tags/rel_1/rtl/verilog
32	Stupid bug that was entered by previous update fixed.	mohor	8227d 19h	/dbg_interface/tags/rel_1/rtl/verilog
31	trst synchronization is not needed and was removed.	mohor	8227d 20h	/dbg_interface/tags/rel_1/rtl/verilog
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8239d 01h	/dbg_interface/tags/rel_1/rtl/verilog
28	TDO and TDO Enable signal are separated into two signals.	mohor	8274d 21h	/dbg_interface/tags/rel_1/rtl/verilog
27	Warnings from synthesys tools fixed.	mohor	8288d 22h	/dbg_interface/tags/rel_1/rtl/verilog
26	Warnings from synthesys tools fixed.	mohor	8288d 22h	/dbg_interface/tags/rel_1/rtl/verilog
25	trst signal is synchronized to wb_clk_i.	mohor	8289d 19h	/dbg_interface/tags/rel_1/rtl/verilog
23	Trace disabled by default.	mohor	8296d 23h	/dbg_interface/tags/rel_1/rtl/verilog
22	Register length fixed.	mohor	8296d 23h	/dbg_interface/tags/rel_1/rtl/verilog

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[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 45

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