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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 92

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Rev Log message Author Age Path
92 temp version. mohor 7476d 19h /dbg_interface/tags/rel_19/bench
91 tmp version. mohor 7477d 14h /dbg_interface/tags/rel_19/bench
90 tmp version. mohor 7478d 09h /dbg_interface/tags/rel_19/bench
89 temp4 version. mohor 7479d 15h /dbg_interface/tags/rel_19/bench
88 temp3 version. mohor 7480d 10h /dbg_interface/tags/rel_19/bench
87 tmp2 version. mohor 7481d 15h /dbg_interface/tags/rel_19/bench
80 New version of the debug interface. Not finished, yet. mohor 7494d 13h /dbg_interface/tags/rel_19/bench
75 Simulation files. mohor 7555d 11h /dbg_interface/tags/rel_19/bench
73 CRC logic changed. mohor 7555d 11h /dbg_interface/tags/rel_19/bench
63 Three more chains added for cpu debug access. simons 7611d 13h /dbg_interface/tags/rel_19/bench
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 12h /dbg_interface/tags/rel_19/bench
38 Few outputs for boundary scan chain added. mohor 8145d 13h /dbg_interface/tags/rel_19/bench
36 Structure changed. Hooks for jtag chain added. mohor 8149d 12h /dbg_interface/tags/rel_19/bench
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8289d 15h /dbg_interface/tags/rel_19/bench
15 bs_chain_o added. mohor 8291d 16h /dbg_interface/tags/rel_19/bench
13 Signal names changed to lowercase. mohor 8292d 17h /dbg_interface/tags/rel_19/bench
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8293d 17h /dbg_interface/tags/rel_19/bench
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8314d 13h /dbg_interface/tags/rel_19/bench
9 Working version. Few bugs fixed, comments added. mohor 8318d 17h /dbg_interface/tags/rel_19/bench
6 Minor changes for simulation. mohor 8319d 15h /dbg_interface/tags/rel_19/bench

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