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[/] [dbg_interface/] [tags/] [rel_21/] - Rev 128

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Rev Log message Author Age Path
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7532d 08h /dbg_interface/tags/rel_21
126 run_sim.scr renamed to run_sim for VATS. mohor 7535d 08h /dbg_interface/tags/rel_21
124 Display for VATS added. mohor 7537d 04h /dbg_interface/tags/rel_21
123 All flipflops are reset. mohor 7537d 04h /dbg_interface/tags/rel_21
121 Port signals are all set to zero after reset. mohor 7540d 05h /dbg_interface/tags/rel_21
120 test stall_test added. mohor 7540d 07h /dbg_interface/tags/rel_21
119 cpu_stall_o activated as soon as bp occurs. mohor 7540d 08h /dbg_interface/tags/rel_21
117 Define name changed. mohor 7542d 04h /dbg_interface/tags/rel_21
116 Data latching changed when testing WB. mohor 7542d 04h /dbg_interface/tags/rel_21
115 More debug data added. mohor 7542d 08h /dbg_interface/tags/rel_21
114 CRC generation iand verification in bench changed. mohor 7542d 09h /dbg_interface/tags/rel_21
113 IDCODE test improved. mohor 7542d 10h /dbg_interface/tags/rel_21
112 dbg_tb_defines.v not used. mohor 7543d 05h /dbg_interface/tags/rel_21
111 Define tap_defines.v added to test bench. mohor 7543d 05h /dbg_interface/tags/rel_21
110 Waiting for "ready" improved. mohor 7543d 06h /dbg_interface/tags/rel_21
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7543d 11h /dbg_interface/tags/rel_21
106 Sensitivity list updated. simons 7544d 09h /dbg_interface/tags/rel_21
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7545d 00h /dbg_interface/tags/rel_21
102 New version. mohor 7545d 00h /dbg_interface/tags/rel_21
101 Almost finished. mohor 7545d 01h /dbg_interface/tags/rel_21

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