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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 158

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158 root 5584d 20h /dbg_interface/tags/rel_21/bench/verilog
134 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7406d 23h /dbg_interface/tags/rel_21/bench/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7451d 06h /dbg_interface/tags/rel_21/bench/verilog
124 Display for VATS added. mohor 7456d 02h /dbg_interface/tags/rel_21/bench/verilog
121 Port signals are all set to zero after reset. mohor 7459d 02h /dbg_interface/tags/rel_21/bench/verilog
120 test stall_test added. mohor 7459d 05h /dbg_interface/tags/rel_21/bench/verilog
117 Define name changed. mohor 7461d 02h /dbg_interface/tags/rel_21/bench/verilog
116 Data latching changed when testing WB. mohor 7461d 02h /dbg_interface/tags/rel_21/bench/verilog
115 More debug data added. mohor 7461d 06h /dbg_interface/tags/rel_21/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7461d 07h /dbg_interface/tags/rel_21/bench/verilog
113 IDCODE test improved. mohor 7461d 08h /dbg_interface/tags/rel_21/bench/verilog
112 dbg_tb_defines.v not used. mohor 7462d 03h /dbg_interface/tags/rel_21/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7462d 03h /dbg_interface/tags/rel_21/bench/verilog
110 Waiting for "ready" improved. mohor 7462d 03h /dbg_interface/tags/rel_21/bench/verilog
102 New version. mohor 7463d 22h /dbg_interface/tags/rel_21/bench/verilog
101 Almost finished. mohor 7463d 23h /dbg_interface/tags/rel_21/bench/verilog
99 cpu registers added. mohor 7465d 01h /dbg_interface/tags/rel_21/bench/verilog
96 Working. mohor 7466d 05h /dbg_interface/tags/rel_21/bench/verilog
95 Temp version. mohor 7466d 17h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7468d 05h /dbg_interface/tags/rel_21/bench/verilog

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