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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog] - Rev 95

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Rev Log message Author Age Path
95 Temp version. mohor 7506d 06h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7507d 17h /dbg_interface/tags/rel_21/bench/verilog
92 temp version. mohor 7510d 21h /dbg_interface/tags/rel_21/bench/verilog
91 tmp version. mohor 7511d 16h /dbg_interface/tags/rel_21/bench/verilog
90 tmp version. mohor 7512d 11h /dbg_interface/tags/rel_21/bench/verilog
89 temp4 version. mohor 7513d 17h /dbg_interface/tags/rel_21/bench/verilog
88 temp3 version. mohor 7514d 12h /dbg_interface/tags/rel_21/bench/verilog
87 tmp2 version. mohor 7515d 17h /dbg_interface/tags/rel_21/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7528d 14h /dbg_interface/tags/rel_21/bench/verilog
75 Simulation files. mohor 7589d 12h /dbg_interface/tags/rel_21/bench/verilog
73 CRC logic changed. mohor 7589d 13h /dbg_interface/tags/rel_21/bench/verilog
63 Three more chains added for cpu debug access. simons 7645d 15h /dbg_interface/tags/rel_21/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8123d 14h /dbg_interface/tags/rel_21/bench/verilog
38 Few outputs for boundary scan chain added. mohor 8179d 14h /dbg_interface/tags/rel_21/bench/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8183d 13h /dbg_interface/tags/rel_21/bench/verilog
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8323d 17h /dbg_interface/tags/rel_21/bench/verilog
15 bs_chain_o added. mohor 8325d 18h /dbg_interface/tags/rel_21/bench/verilog
13 Signal names changed to lowercase. mohor 8326d 19h /dbg_interface/tags/rel_21/bench/verilog
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8327d 19h /dbg_interface/tags/rel_21/bench/verilog
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8348d 15h /dbg_interface/tags/rel_21/bench/verilog

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